Recently, various types of digital devices such as smartphones or tablets include numerous semiconductor chips. These semiconductor chips are manufactured in the form of a wafer during a semiconductor fabrication process, divided into chips through a packaging process, and installed in a printed circuit board (PCB) to exhibit functions thereof.
In the past, wafer-type chips were separated one by one and underwent a packaging process so as to be used. Conventionally, packaging methods such as a quad flat package (QFP), a chip scale package (CSP), or a ball grid array (BGA) has been used.
When chips are separately packaged, the chips should be handled individually, and thus, when a pattering operation, or the like, is performed, a problem of chip alignment arises. In addition, recently, chips tend to decrease in size, making it difficult to handle individual chips.
Wafer level packaging (WLP) is a method for overcoming such a problem. The WLP is a method of performing packaging entirely without separating chips from a wafer or rearranging chips in a wafer form and performing packaging thereon. After packaging is completed through this method, a dicing process is performed to dice chips one by one to use the chips. In this manner, the packaging process is simplified, a chip size after packaging is reduced, and an area of the chips mounted on a printed circuit board (PCB) is also reduced, remarkably improving the semiconductor assembly process.
Packages have been reduced in through the WLP, and recently, a chip scale package (CSP) in which a package size is substantially equal to a chip size has also been developed.
However, recently, as mobile markets such as smartphones, tablet PCs, or portable game devices have grown, it is required to further reduce a chip size, while the number of input/output (JO) terminals of chips tend to rather increase, rather than being reduced, and thus, there is limitations in coping with such demand with an existing fan-in type package such as the CSP.
The related art CSP is called a fan-in type CSP because an array of solder balls for input/output is not larger than a chip size. However, due to the development of fabrication technologies, chip sizes have been decreased, while the number of input/output terminals of chips have remain the same or rather increased for enhancement of performance, and thus, the fan-in type packages cannot support the increased number of input/output terminals, namely, the number of solder balls, in some cases.
As a solution, a wafer level package in which a region where solder balls are disposed is greater than a chip size has been developed, which is called a fan-out type wafer level package.
FIG. 1 is a flow of an existing process.
For a fan-out type package, spaces between chips need to be increased as much. However, spaces between chips in a wafer state are narrow, and thus a process of separating the chips in the wafer state and rearranging the separated chips to make the chips in a wafer form is additionally required.
In the existing fan-out wafer level package process, a double-sided tape for fixing chips is attached to a mother substrate (also called a sacrificial substrate or a parasitic substrate), and chips separated from a wafer are rearranged one by one.
Wafer level molding is performed on the rearranged chips. This is to fill a solder ball region wider than the chips, and in general, the solder ball region is filled using a mold compound. After chips are attached to the molding, a carrier removal/debonding step is performed to separate the mother substrate from the chips and the molding.
Thereafter, a general wafer level packaging the same as the related art fan-in packaging is performed. That is, general processes such as passivation for insulation or chip protection, patterning, re-distribution layer (RDL), and bonding are performed.
However, in spite of the aforementioned advantages, the existing fan-out level packaging has not been widely used due to problems too serious for actual mass-production. Typical problems thereof include chip alignment, warpage of wafer, and contamination.
A robot is used at the stage of rearranging chips on a mother substrate, and here, since it is not possible to adjust precision of the robot to a few micro scale, aligning chips in a wafer level after chip arrangement may have a problem, leading to difficulty in patterning or RDL.
Also, even though chips are properly aligned on a mother substrate, a mold compound used for molding is deformed due to contraction and expansion thereof, which is fatal in a packaging process requiring precision. In addition, particles of the mold compound may degrade production yield and contaminate chips.
Due to the aforementioned problems, a speed of fan-out wafer level packaging slows to obstruct mass-production.